Integrated antifuse structure for finfet and cmos devices

ABSTRACT

A method is described for fabricating and antifuse structure ( 100 ) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material ( 11 ) is provided overlying an insulator ( 3 ) disposed on a substrate ( 10 ); an etching process exposes a plurality of corners ( 111 - 114 ) in the semiconducting material. The exposed corners are oxidized to form elongated tips ( 111   t - 114   t ) at the corners; the oxide ( 31 ) overlying the tips is removed. An oxide layer ( 51 ), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material ( 60 ) is formed in contact with the oxide layer ( 51 ) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path ( 103, 280 ).

TECHNICAL FIELD

This invention relates to the manufacture of very large-scale integrateddevices, particularly FINFET and planar CMOS devices, with electricalantifuses integrated therein.

BACKGROUND ART

In their ongoing effort to obtain smaller, faster and more efficientsemiconductor devices, designers and engineers have attempted to reducethe scale of all the dimensions and features of the devices. In thedesign and manufacture of field-effect transistors (FETs) particularly,it has been found that two features are difficult to scale down: thedevice current (which is related to the size of the FET gate) and thesize of fuse structures.

To address device scaling limitations in gate design, considerable workhas recently been done to develop manufacturable methods to create noveltypes of gates. One example of a “dual gate” or “wrap-around gate”design is the FINFET device, where the gate oxide is grown on the faceof a vertical fin of silicon and the gate is on both sides of thesilicon feature, which when activated fully depletes the silicon. FIG.1A shows two such fin structures 1, 2 formed on a silicon-on-insulator(SOI) substrate, where the top of the bulk silicon substrate 10 has aburied oxide (BOX) layer 3 formed thereon, and the devices are made in afurther silicon layer overlying the BOX. Silicon fins 11, 21 are shownafter being formed by etching of this silicon layer down to the BOXsurface, using an etching hardmask 12, 22 for image transfer. A gateoxide may then be grown on both faces of a silicon fin (such as faces 11a and 11 b of fin 11). The FINFET technology shows promise in offeringhigher areal gate density than more conventional planar CMOS devices, aswell as better device performance, and lower power consumption.

It is also desirable to incorporate the manufacture of fuses andantifuses into existing processes for creating the various FETstructures. As is known in the art, fuses are conductors which mayeasily be removed (“blown”) to create open circuits, while antifuses areareas of dielectric which may be electrically broken down to form apermanent conducting path. As the density of devices on a chipincreases, the number of fuses and antifuses increases in order toprovide specific addressing of each individual circuit. Fuses andantifuses are preferably formed with minimal expense of chip area andrequire no additional lithographic steps. Recent scaling of fuses hasnot kept up with the scaling rate of the rest of the silicon features,so that chip regions devoted to fuses are occupying a larger percentageof the total chip area.

If devices are formed with shallow-trench isolation (STI), etching ofthe isolation trench may create sharp corners in the silicon where thesidewall of the trench meets the top silicon surface or the trenchbottom. If these corners are not rounded by further processing, adielectric layer overlying the corners may be thinned and presentreliability problems (see U.S. Pat. No. 6,150,234). Similarly, etchingof a contact hole through a dielectric layer may result in a trench withsharp corners. On the other hand, a sharp trench corner presents anopportunity to conveniently form antifuses (the trench being etched in aconductive material or being coated with a conductive material), sincethe electric field is generally enhanced at the corner; while aninsulating layer overlying the corner is thinned (see U.S. Pat. No.5,502,000; U.S. Pat. No. 5,322,812; U.S. Pat. No. 6,096,580 andreferences cited therein; and Chen et al., IEEE Electron Device Letters13, 53 (1992)).

Because significantly less chip area is required, it is preferable tofabricate electrical fuses rather than mechanical fuses as part of thetransistor fabrication process. Conventional fuses are “blown” via laserablation or other mechanical means to create an electrical open.Electrical fuses or antifuses are “blown” via internal electrical wiringin the chip; the area requirement for electrical fuses/antifuses istherefore much less. In addition, mechanical fuses require a protectionregion around and below them, to prevent the fuse-blowing technique fromhaving other detrimental impacts on the chip circuits. Electrical fusesand antifuses do not have this requirement. To save chip area and thusreduce manufacturing cost, it therefore is desirable to fabricateelectrical fuses or antifuses which may be integrated with fabricationof FINFET and planar CMOS devices, with a minimum number of additionalfabrication steps.

DISCLOSURE OF INVENTION

The present invention addresses the above-described need by providing amethod for fabricating an antifuse structure integrated with asemiconductor device, with a minimum of additional process steps. Aregion of semiconducting material is provided overlying an insulatordisposed on a substrate; an etching process exposes a plurality ofcorners in the semiconducting material. The exposed corners are oxidizedto form elongated tips at the corners; the oxide overlying the tips isremoved. An oxide layer, such as a gate oxide, is then formed on thesemiconducting material and overlying the corners; this layer has areduced thickness at the corners. A layer of conducting material isformed in contact with the oxide layer at the corners, thereby forming aplurality of possible breakdown paths between the semiconductingmaterial and the layer of conducting material through the oxide layer.Applying a voltage, such as a burn-in voltage, to the structure convertsat least one of the breakdown paths to a conducting path, when it isdesired to activate a specific antifuse electrically.

This process may be practiced with FINFET or planar CMOS devices, sothat the antifuse structures are integrated with those devices.

It is noteworthy that the antifuse structures fabricated with thisprocess each have a plurality of possible breakdown paths which areelectrically in parallel. A conducting path may be formed by breakingdown the oxide layer at any of these paths. This redundancy helps toensure that the device will be programmable. The applied voltage istypically about 1.5 times the nominal voltage for the device.

Furthermore, in accordance with the present invention, an antifusestructure is provided which is integrated with a semiconductor device.The antifuse structure includes a region of semiconducting materialoverlying an insulator disposed on a substrate; the semiconductingmaterial has a plurality of corners with a plurality of elongated tipsof the semiconducting material at the respective corners. An oxide layeris disposed on the semiconducting material and overlying the corners;the oxide layer has a nominal thickness and a reduced thickness at thecorners less than the nominal thickness. The structure also includes alayer of conducting material in contact with the oxide layer at thecorners. A feature of the structure is that a plurality of possiblebreakdown paths are disposed at the corners, between the semiconductingmaterial and the layer of conducting material through the reducedthickness of the oxide layer.

It is also noteworthy that the antifuse structures are integrated at thesilicon level, and accordingly require minimal chip area. Thefabrication process for the antifuses requires only one additionalmasking layer, relative to the standard transistor fabricationprocesses.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A-1G are schematic illustrations of steps in a fabricationprocess for integrated antifuses in a FINFET device, in accordance witha first embodiment of the invention.

FIGS. 2A-2E are schematic illustrations of steps in a fabricationprocess for integrated antifuses in a planar CMOS device, in accordancewith a second embodiment of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

In accordance with the present invention, a plurality of antifuses isformed at a semiconducting gate structure by oxidation of exposedcorners. This process may be applied to either FINFET or planar CMOSgate structures, as detailed below.

(1) Antifuses for FINFET Devices

FIG. 1A shows two neighboring silicon fins 11, 21 which may form thebodies of FINFETs after gate electrode processing. In this illustration,one of these (fin 11) is instead made into an antifuse structure. Thefin structure 2, which includes fin 21 and hardmask 22, is coated with aprotective layer of resist 25; the resist is exposed and developed touncover fin structure 1. The exposed portion of the BOX layer 3 is thensubjected to an isotropic etch which undercuts silicon fin 11 (see FIG.1B). The hardmask 12 is also removed in this step. It should be notedthat the etching and undercutting results in four exposed corners111-114 on silicon fin 11.

The silicon surface of fin 11 is then oxidized in a low-temperatureoxidation process, to form an oxide layer 31 thereon. The oxidationprocess is preferably a dry/wet/dry process at 900° C., which is knownto those skilled in the art. During the oxidation process,two-dimensional stresses at the corners 111-114 result in formation ofelongated tips of silicon 111 t, 112 t, 113 t, 114 t, shown on anexaggerated scale in FIG. 1C. These tips are created during oxidation asthe stress in the oxide film at the corners reduces the oxygen diffusionrate. Oxide layer 31 is then removed in an isotropic etch process, afterwhich resist 25 is stripped (see FIG. 1D).

An n+ ion implantation may be advantageously performed into the fuseregion before resist 25 is removed. Although not required foroperability of the structure as an antifuse, this implantation processmakes the silicon portion of the fuse an improved conductor, andimproves the performance of the fin in terms of required programmingvoltage and reliability.

A standard gate oxide preclean is then performed on both silicon fins 11and 21, after which a gate oxide 51, 52 is grown on the exposed surfacesof fins 11 and 21 respectively. The thickness of the gate oxide istypically in the range 15-40 Å. A polysilicon conductor layer 60 is thendeposited over the fins; this polysilicon layer serves as the gateconductor for the FINFET 200, while providing a conducting path in theantifuse 100. A resist layer 65 is deposited over both structures andpatterned to define the transistor gates, as well as one node of thefuse. As shown in FIG. 1E, opening 66 separates the two types ofstructures. The portion of polysilicon layer 60 exposed in this openingis then etched, and resist 65 is stripped away. The FINFET structure 200and the antifuse structure 100 are thus electrically isolated from eachother (see FIG. 1F).

FIG. 1G is a detail view showing the gate oxide 51 overlying the cornersof fin 11 having tips 111 t, 112 t, 113 t, 114 t, with a reducedthickness at the corners (tips) relative to the nominal thicknessthereof. The tips at the corners are shown in an exaggerated fashion forthe purposes of illustration; actual thinning of the oxide isapproximately 15%-30% as compared with the oxide covering the centralarea on the face of the fin. The tips in FIG. 1G are shown only incross-section; it should be understood that an elongated tip is formedalong the edge of the fin, so that sharp ridges run the length of thefin, normal to the plane of the figure. It should be noted that in FIG.1G there are four possible breakdown paths across the thinned oxide, sothat there is built-in redundancy in the antifuse design. All of thesebreakdown paths are electrically in parallel, so that an actualbreakdown of any one of them is sufficient to convert the antifuse intoan electrical short, which can be used to reroute data or instructionsin the chip. A programming or writing operation for the antifuse (thatis, converting the antifuse into a conducting path) thus comprisesapplying a voltage sufficient to cause breakdown at one of the corners(such as corner 113 in FIG. 1G, creating breakdown path 103). It hasbeen found that the writing operation can be performed effectively usingthe burn-in voltage for the FET devices, which is typically 1.5 timesthe nominal voltage. For example, with a nominal voltage of about 1.2 V,the burn-in voltage would be about 1.8 V. Accordingly, a writingoperation on the antifuse may be performed at burn-in voltages withoutadversely affecting the normal operation of the other devices on thechip.

(2) Antifuses for Planar CMOS Devices

The essential features of the above-described method may be adapted toplanar CMOS devices fabricated on SOI substrates. FIG. 2A shows threesilicon gate regions 211, 212, 213, where region 211 is to be made intoan antifuse instead of a FET. The silicon regions are disposed on aburied oxide (BOX) 203 on substrate 210, and are separated by shallowtrench isolation regions (STI) 215. A resist layer 205 is deposited overall the silicon regions, and then patterned so that an opening 220 inthe resist exposes silicon region 211 and portions of isolation regions215 which are to be fabricated into an antifuse. The STI material 215(typically oxide) is then etched, in order to expose corners 211 a, 211b of silicon region 211.

A low-temperature oxidation process is then performed so that theexposed silicon surface is covered by an oxide layer 231, as shown inFIG. 2B. This oxidation process causes formation of silicon tips 211 tat the corners, as shown in FIG. 2C. As noted above, the tips are shownonly in cross section; sharp ridges run the length of region 211 normalto the plane of the figure. The oxide layer 231 is then removed using anisotropic etch process. At this point it is preferred, but not required,that silicon region 211 (which will become the antifuse) be implantedwith an n+ dopant, in order to facilitate programming (writing) of theantifuse. Resist 205 is then removed.

A standard preclean is then performed and a gate oxide 251, 252, 253 isgrown on the surface of silicon regions 211, 212, 213 respectively (seeFIG. 2D). This gate oxide is typically 10-20 Å thick. A polysiliconlayer 260 is deposited on all the silicon and isolation regions. Thislayer is then patterned with the transistor gate images, as well asdefining one node of the antifuse, and etched so that openings 266 areformed over the isolation regions 215, electrically isolating the MOSdevice regions from the antifuse and from each other.

FIG. 2E is a detail view of the antifuse structure for planar CMOSdevices. The thinning of the gate oxide near the tips 211 t isexaggerated for purposes of illustration; the gate oxide at thislocation is typically 15% to 30% thinner than at the central area of theantifuse (that is, layer 251 has a reduced thickness at the corners 15%to 30% less than the nominal thickness of 10-20 Å). Since at least twoexposed corners of the silicon have been oxidized, there are at leasttwo potential breakdown paths between the doped silicon region 211 andthe polysilicon conductor 260. Programming (writing) the antifuse usinga voltage as low as the burn-in voltage creates conducting path 280,shown schematically in FIG. 2E.

INDUSTRIAL APPLICABILITY

The present invention is generally applicable to the problem offabricating field-programmable gate arrays which are often required forapplication-specific integrated circuits (ASICs). In addition, antifusescan be used to re-route data for redundancy, such as in memory circuits,or in advanced microprocessors. In particular, the invention isapplicable to gate arrays or SRAMs employing FINFET or planar CMOStechnology. An important advantage of the invention is that redundantbreakdown points are provided at each antifuse location. In addition,the antifuse fabrication process requires only one additional maskinglayer relative to the standard transistor fabrication process.Furthermore, the antifuses are fabricated at the silicon level (that is,during the process of building the neighboring transistors), resultingin significant saving of area on the chip.

While the present invention has been described in terms of specificembodiments, it is evident in view of the foregoing description thatnumerous alternatives, modifications and variations will be apparent tothose skilled in the art. Accordingly, the invention is intended toencompass all such alternatives, modifications and variations which fallwithin the scope and spirit of the invention and the following claims.

1-19. (canceled)
 20. A method for fabricating an antifuse structureintegrated with a semiconductor device, the method comprising the stepsof: forming a region of semiconducting material overlying an insulatordisposed on a substrate; performing an etching process to expose aplurality of corners in the semiconducting material; forming a pluralityof elongated tips of the semiconducting material at the respectivecorners by oxidizing the exposed corners to form an oxide thereon andthen removing the oxide; subsequently forming an oxide layer on thesemiconducting material and overlying the corners, the oxide layerhaving a nominal thickness and a reduced thickness at the corners lessthan the nominal thickness; and forming a layer of conducting materialin contact with the oxide layer at the corners, thereby forming aplurality of possible breakdown paths at said corners, between thesemiconducting material and the layer of conducting material through theoxide layer.
 21. A method according to claim 20, wherein the region ofsemiconducting material is a fin formed in a FINFET process.
 22. Amethod according to claim 20, wherein the region of semiconductingmaterial is a gate region formed in a planar CMOS process.
 23. A methodaccording to claim 21 or claim 22, further comprising the step of dopingthe region of semiconducting material.
 24. A method according to claim20, wherein oxidizing the exposed corners is performed in accordancewith a low-temperature oxidation process.
 25. A method according toclaim 20, wherein the breakdown paths are electrically in parallel. 26.A method according to claim 20, further comprising the step of applyinga voltage to the antifuse structure, thereby converting at least one ofthe breakdown paths to a conducting path through the oxide layer.
 27. Amethod according to claim 26, wherein the voltage is applied inaccordance with a burn-in process for the device.
 28. A method accordingto claim 26, wherein the device has a nominal voltage, and the appliedvoltage is approximately 1.5 times the nominal voltage.
 29. An antifusestructure integrated with a semiconductor device, the structurecomprising: a region of semiconducting material overlying an insulatordisposed on a substrate, the semiconducting material having a pluralityof corners with a plurality of elongated tips of the semiconductingmaterial at the respective corners; an oxide layer on the semiconductingmaterial and overlying the corners and in contact with the corners, theoxide layer having a nominal thickness and a reduced thickness at thecorners less than the nominal thickness; and a layer of conductingmaterial in contact with the oxide layer at the corners, wherein aplurality of possible breakdown paths are disposed at said corners,between the semiconducting material and the layer of conducting materialthrough the reduced thickness of the oxide layer, and the elongated tipsare formed by oxidation of the exposed corners, the oxide formed therebybeing different from the oxide layer.
 30. An antifuse structureaccording to claim 29, wherein the region of semiconducting material isa fin formed in a FINFET process.
 31. An antifuse structure according toclaim 29, wherein the region of semiconducting material is a gate regionformed in a planar CMOS process.
 32. An antifuse structure according toclaim 29, wherein the region of semiconducting material is a region ofdoped material.
 33. An antifuse structure according to claim 29, whereinthe breakdown paths are electrically in parallel.
 34. An antifusestructure according to claim 29, wherein at least one of the breakdownpaths is a conducting path through the oxide layer formed by applicationof a voltage thereto.
 35. An antifuse structure according to claim 34,wherein the applied voltage is a burn-in voltage for the device.
 36. Amethod according to claim 34, wherein the device has a nominal voltage,and the applied voltage is approximately 1.5 times the nominal voltage.